The present invention relates to a semiconductor device and a technique for manufacturing the same. Particularly, the present invention is concerned with a technique which is effectively applicable to a multi-chip module (MCM) with plural types of semiconductor chips of different terminal pitches mounted on a wiring substrate.
As a measure for increasing the capacity of memory LSIs such as flash memory and DRAM (Dynamic Random Access Memory), various memory module structures have been proposed in which semiconductor chips (memory chips) with such memory LSIs formed thereon are stacked and sealed in a single package.
For example, Japanese Published Unexamined Patent Application No. Hei 4(1992)-302164 discloses a package structure wherein plural semiconductor chips of the same function and same size are stacked stepwise through an insulating layer within a single package and bonding pads exposed to stepped portions of the semiconductor chips and inner leads of the package are electrically connected together through wires.
In Japanese Published Unexamined Patent Application No. Hei 11(1999)-204720 there is disclosed a package structure wherein a first semiconductor chip is mounted on an insulating substrate through a thermocompression bonding sheet, a second semiconductor chip having an external size smaller than that of the first semiconductor chip is mounted on the first semiconductor chip through an insulating sheet, bonding pads of the first and second semiconductor chips and a wiring layer on the insulating substrate are electrically connected together through wires, and the first and second semiconductor chips and the wires are sealed with resin.
Also known is a technique called Wafer Level CSP (Chip Size Package) or Wafer Process Package (WPP) wherein solder bumps are arranged in an array form on a main surface of a semiconductor chip and bonding pads and the solder bumps are electrically connected together through wires formed of Cu (copper) for example, thereby making the pitch of connecting terminals (solder bumps) wider than that of the bonding pads. With this technique, the terminal pitch of the semiconductor chip can be substantially widened, so that even without using an expensive build-up substrate with narrowed line and space of wires, it is possible to fabricate a memory module with use of a less expensive resin substrate having a wide wiring pitch. As to Wafer Level CSP, related descriptions are found, for example, in “Electronics Mounting Technique: 2000 Extra Edition,” pp. 81 to 113, published by Kabushiki Kaisha TECHNICAL RESEARCH COUNCIL (May 28, 2000), and also in International Patent Publication WO99/23696.